1. Field of Invention
The present invention pertains to the field of memory sense amplifiers. More particularly, this invention relates to memory differential sense amplifiers having adjustable sense and reference circuitry.
2. Background
In a random access memory (RAM) array, an amplifier is used to sense the state of an addressed memory cell and provide a signal representing the sensed state to the output of the array. This sense amplifier takes different forms, depending on the type of RAM array. In a static random access memory (SRAM) array or dynamic random access memory (DRAM) array, the memory is often volatile, that is, not retaining the data when the array is powered off. Such memories are often complex and require complex sensing circuitry such as steering (decoder) circuits and clocked, current mode amplifiers.
In contrast, a non-volatile memory array, such as a cross-point array, utilizes very simple compact memory cells, such as the cross-point type, concerned with long-term retention, high density and fast access. A non-volatile array may be a write-once type having a fuse or anti-fuse at each cross-point cell, or a multiple read-write variety, such as a magnetic random access memory (MRAM) array having cross-point magnetic cells each capable of changing between two or more states.
One problem with resistive memory arrays, such as arrays using MRAM cells, is the difficulty in accurately determining the logic state of a memory cell. This problem arises because the cell states are not measured by conductance or non-conductance, as in an anti fuse memory. Rather the MRAM cell states are determined by minute differences in the conductivity of a thin insulating junction embedded within the MRAM memory cell caused by the relative direction of the magnetization of ferromagnetic layers adjacent to the thin insulating junction. Typically, the states of an MRAM cell are determined by a data magnetic layer having a magnetic moment either xe2x80x9cparallelxe2x80x9d or xe2x80x9canti-parallelxe2x80x9d relative to a fixed magnetic layer. The states are measured by a difference in the resistance caused by the magnetism of the data layer being xe2x80x9cparallelxe2x80x9d or xe2x80x9canti-parallelxe2x80x9d to the fixed layer. This resistance is sensed by the current flow through the insulation layer and the magnitude of the sense current is typically on the order of 500 nA, and the difference in the current between the xe2x80x9cparallelxe2x80x9d and the xe2x80x9canti-parallelxe2x80x9d states is typically about 50 nA.
Accordingly, it is crucial to carefully sense small variations in the sensed current through a selected memory cell, in order to accurately determine the logic state of the cell. One common sense amplifier is a current mode sense amplifier where the memory cell current must be sensed by a circuit that depends on a precision current mirror as part of the sense amplifier. Thus, for current mode sense amplifiers, it is also important to provide an accurate xe2x80x9cmirrorxe2x80x9d of the sensed current from the cell to the sense amplifier, as well as to provide a means of measuring the sensed current against a reliable standard to determine the state of the cell.
In addition, there is a greater need for higher density memory devices to meet the memory requirements of increasingly complex devices. This demand has lead to increased miniaturization and more compact data storage than ever before. Efforts are now underway to adapt technology to enable the storage of data on a scale of nanometers to tens of nanometers, sometimes referred to as atomic resolution storage. This size reduction and compactness of memory devices requires smaller voltages and currents, resulting in the need for greater preciseness in measuring the currents and voltages to accurately determine the data in the cell.
In dealing with miniaturized circuits and extremely small currents and voltages, it is important to minimize the intrusive nature of the sensing function. Each element that is used in a sensing circuit may contribute to voltage and current distortions or leakages that will have an impact on the measurement accuracy of the sensor. Accordingly, it is imperative that a sense amplifier for high-density memory cells must minimize any intrusions into the memory matrix that could result in adverse affects on the parameters being sensed.
Voltage mode sense amplifiers sometimes require complex circuitry to achieve accuracy. For example, one voltage mode differential amplifier requires five transistors in a complex circuit to carry out the necessary sensing, as seen in U.S. Pat. No. 6,262,625, granted to Perner et al. on Jul. 17, 2001. In that circuit, back gate digital controlled voltages are applied to a pair of transistors so that the sense amplifier offset parameters may be incrementally adjusted. Back gate digital control values are stored in a register memory to control the precision of the sense amplifier, further increasing the complexity of the sensing circuit.
Current mode sense amplifiers are sometimes used for high density, sensitive memory matrix sensing. However, current mode sense amplifiers tend to require a high level of component matching because of the limited dynamic range of such a circuit. If the current of the reference cell is substantially different than the current of the memory cell being sensed, the current mode sense amplifier may not be able to accurately determine the logic state of the memory cell. Adding components, such as additional sense resistors, may compensate for this limited range problem. However, the addition of components to a current sense circuit tends to adversely affect the circuits being sensed.
Other sense amplifiers use analog to digital conversion (ADC) to measure the sense and reference currents and compare them digitally. This approach is useful in extending the dynamic range of the components. However, the increased complexity of the sensing circuit is an important disadvantage.
Accordingly, a simple sensing amplifier is needed for measuring memory cell matrices at very low levels of sense currents and voltages. Sensing components are needed that will accurately mirror the sense parameters and reflect them to the sensing circuit. In addition, a sense amplifier is needed that uses a small number of components so that the intrusion into a memory matrix is minimized. Finally, it is important that a sensing amplifier have a relatively wide dynamic range for accommodating different levels of currents and voltages.
The present invention provides a useful and unique sensing circuit in the nature of an adjustable current mode differential sense amplifier. The amplifier is in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell.
The operating point of the sensing amplifier may be changed by modifying the threshold voltage of isolated transistors in the sense amplifier. This is accomplished in a non-invasive manner by applying a control voltage on back gate electrodes of the isolated transistors. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier. When a second bias voltage is applied to the memory and reference cells in order to determine the memory cell value, the amplifier is able to sense slight changes in the currents or voltages associated with the selected memory cell and the reference cell and compare them to determine the state of the memory cell. This increased sensitivity enables the amplifier to have a substantially increased dynamic range without introducing components that might adversely affect the memory circuitry parameters.
An apparatus embodiment of the present invention comprises a sensing circuit for determining the logic state of a memory cell in a resistive memory device. The circuit includes a reference cell having a pre-selected logic state. A memory cell sensing circuit is adapted to determine a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and to determine a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell. A reference cell sensing circuit is adapted to determine a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and to determine a second reference voltage associated with the reference cell when the second biasing voltage is impressed on the reference cell. An adjusting circuit is used to modify either the first reference cell voltage or the first memory cell voltage so that the first reference cell voltage is equal to the first memory cell voltage at the first bias voltage. A state determining circuit is disposed to sense the difference between the second memory cell voltage and the second reference cell voltage at the second bias voltage in order to determine the logic state of the memory cell.
Similar to the above apparatus embodiment, a method embodiment of the present invention is a method for determining the logic state of a memory cell in a resistive memory device, using a reference cell previously set to a known logic state. The method comprises determining the logic state of a memory cell in a resistive memory device relative to a reference cell having a pre-selected logic state. A first memory cell voltage associated with the memory cell and a first reference cell voltage associated with the reference cell are sensed when a first bias voltage is impressed on the memory cell and the reference cell. The first memory cell voltage or the first reference cell voltage is then adjusted using a non-invasive back gate control voltage so that the first reference cell voltage and the first memory cell voltage are approximately equal to each other. Next, a second memory cell voltage associated with the memory cell and a second reference cell voltage associated with the reference cell are sensed when a second bias voltage is applied to the memory cell and to the reference cell. Then the difference between the second memory cell voltage and the second reference cell voltage is measured to determine the logic state of the memory cell.
It should be understood that, for both the apparatus and method embodiments described above, rather than sensing and adjusting the first and second memory cell voltages and the first and second reference cell voltages, other parameters associated with the memory cell and reference cell, such as current or resistance, may be sensed and adjusted in order to determine the state of a selected memory cell. The scope of the present invention is meant to include selecting any parameter associated with the selected memory cell and the reference cell to be sensed and adjusted according to the principles of the present invention.